Digital electronics and logic design sppu mcq pdf (DELD MCQ)

Digital Electronics and Logic Design MCQ

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Digital electronics and logic design sppu mcq (deld mcq) questions with answers are listed down for the online mcq exams conducted by Universities like Pune university, Mumbai University and the University all around. Digital electronics and logic design mcq pdf free for deld mcq questions

Q. The number of canonical expressions that can be developed over a 3-valued boolean algebra is
A. 8
B. 16
C. 32
D. 256

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256

Q. Simplified form of the boolean expression (X + Y + XY) (X + Z) is
A. X + Y + Z
B. XY + YZ
C. X + YZ
D. XZ + Y

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X + Y + Z

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Q. A switching function is symmetric with respect to a set of literals if and only if the function remains unchanged after
A. Two of these literals are interchanged
B. Any permutation of the literals
C. All the literals are changed in anticlockwise order
D. All the literals are changed in clockwise order

Any permutation of the literals

Q. The voltages in digital electronics are continuously variable.
A. True
B. False

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False

Q. One hex digit is sometimes referred to as a(n):
A. byte
B. nibble
C. grouping
D. instruction

nibble

DELD mcq pdf

Q. The minimal cover for the maimal compatibility classes {ae, acd, ad, bd} is
A. ae, acd, ad ‘
B. acd, ad, bd
C. ae, acd, bd
D. ae, ad, bd

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ae, ad, bd

Q. Which of the following expression remove hazard from : xy + zx ‘ ?
A. xy+zx’
B. xy+zx ‘+wyz
C. xy+zx’+yz
D. xy + zx’ + wz

xy+zx’+yz

Q. What is the form of the boolean expressions AB+ B’C’ =Y?
A. Product-of-sums
B. Sum-of-products
C. Karnaugh map
D. Matrix

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Sum-of-products

Q. How many boolean functions of three variables f(x, y, z) have the property that f(x, y, z) = (f(x, y, z)) ?
A. 8
B. 6
C. 64
D. 26

6

Q. A graphical display of the fundamental products in a truth-table is known as
A. Mapping
B. Graphing
C. T-map
D. karnaugh-map

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karnaugh-map

Q. Which is typically the longest: bit, byte, nibble, word?
A. Bit
B. Byte
C. Nibble
D. Word

Word

Q. How many binary digits are required to count to 10010?
A. 7
B. 2
C. 3
D. 100

7

Q. Consider following switching function: f(w, x, y, z) = w’x’ + w’x y’+ wx’z’+ wxy For this function, which of the following is list of essential prime impicants ?
A. w’ x’, w’ y’, x’ y’, wxy, wyz
B. wxy, wyz’
C. w’ x’, w’ y’, x’ z’
D. w’ x’, w’ y’, x’ z, wxy’

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w’ x’, w’ y’, x’ z’

Q. If set x = {a, b, c, d}, then number of binary operations that can be defined on x is
A. 42
B. 24
C. 216
D. 416

216

Q. The minimum number of NAND gates required to implement the Boolean function. A + AB’ + AB’C is equal to
A. zero
B. 1
C. 4
D. 7

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zero

Q. Which of the following logic expression is incorrect?
A. 1 ⊕ 0 = 1
B. 1 ⊕ 1 ⊕ 0 =1
C. 1 ⊕ 1 ⊕ 1 = 1
D. 1 ⊕ 1 = 0

1 ⊕ 1 ⊕ 0 =1

Q. In which of the following gates, the output is 1, if and only if at least one input is 1?
A. NOR
B. AND
C. OR
D. NAND

OR

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Q. What is the minimum number of two-input NAND gates used to perform the function of two input OR gate ?
A. one
B. two
C. three
D. four

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three

Digital electronics and logic design mcq

Q. Odd parity of word can beconveniently tested by
A. OR gate
B. AND gate
C. NOR gate
D. XOR gate

XOR gate

Q. Which one of the following will give the sum of full adders as output ?
A. Three point majority circuit
B. Three bit parity checker
C. Three bit comparator
D. Three bit counter

Three bit counter

Q. The number of full and half-adders required to add 16-bit numbers is
A. 8 half-adders, 8 full-adders
B. 1 half-adder, 15 full-adders
C. 16 half-adders, 0 full-adders
D. 4 half-adders, 12 full-adders

1 half-adder, 15 full-adders

Q. The time required for a pulse to decrease from 90 to 10 per cent of its maximum value is called
A. Rise time
B. Decay time
C. Binary level transition period
D. Propagation delay

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Decay time

Q. Which of the following gates would output 1 when one input is 1 and other input is 0 ?
A. OR gate
B. AND gate
C. NAND gate
D. both (a) and (c)

both (a) and (c)

Q. The sum of 11101 + 10111 equals __.
When using even parity, where is the parity bit placed?

A. Before the MSB
B. After the LSB
C. In the parity word
D. After the odd parity bit

Before the MSB

Q. Which of the following is an invalid BCD code?
A. 0011
B. 1101
C. 0101
D. 1001

1101

Q. Convert the Gray code 1011 to binary.
A. 1011
B. 1010
C. 0100
D. 1101

1101

Q. Determine the decimal equivalent of the signed binary number 11110100 in
1’s complement.

A. 116
B. –12
C. –11
D. 128

–11

Q. Which of the following statements is wrong ?
A. Propagation delay is the time required for a gate to change its state
B. Noise immunity is the amount of noise which can be applied to the
input of a gate without causing the gate to change state
C. Fan-in of a gate is always equal to fan-out of the same gate
D. Operating speed is the maximum frequency at which digital data can be
applied to a gate

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Fan-in of a gate is always equal to fan-out of the same gate

Q. Which of the following expressions is not equivalent to X ‘ ?
A. X NAND X
B. X NOR X
C. X NAND 1
D. X NOR 1

X NOR 1

Q. Which of the following gates are added to the inputs of the OR gate to convert it to the NAND gate ?
A. NOT
B. AND
C. OR
D. XOR

NOT

Q. The EXCLUSIVE NOR gate is equivalent to which gate followed by an inverter ?
A. OR
B. AND
C. NAND
D. XOR

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XOR

Q. A one-to-four line demultiplexer is to be implemented using a memory. How many bits must each word have ?
A. 1 bit
B. 2 bits
C. 4 bits
D. 8 bits

1 bit

Q. What logic function is produced by adding an inverter to the output of an AND gate ?
A. NAND
B. NOR
C. XOR
D. OR

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NAND

Q. Which of the following gates is known as coincidence detector ?
A. AND gate
B. OR gate
C. NOT gate
D. NAND gate

AND gate

Q. Which table shows the logical state of a digital circuit output for every possible combination of logical states in the inputs ?
A. Function table
B. Truth table
C. Routing table
D. ASCII table

Truth table

Q. A positive AND gate is also a negative
A. NAND gate
B. NOR gate
C. AND gate
D. OR gate

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OR gate

Q. A demultiplexer is used to
A. Route the data from single input to one of many outputs
B. Perform serial to parallel conversion
C. Both (a) & (b)
D. Select data from several inputs and route it to single output

Both (a) & (b)

Q. An OR gate can be imagined as
A. Switches connected in series
B. Switches connected in parallel
C. MOS transistors connected in series
D. None of these

Switches connected in parallel

Q. Which combination of gates does not allow the implementation of an arbitrary boolean function?
A. OR gates and AND gates only
B. OR gates and exclusive OR gate only
C. OR gates and NOT gates only
D. NAND gates only

OR gates and exclusive OR gate only

Q. How many full adders are required to construct an m-bit parallel adder ?
A. m/2
B. m-1
C. m
D. m+1

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m-1

Q. Parallel adders are
A. combinational logic circuits
B. sequential logic circuits
C. both (a) and (b)
D. None of these

combinational logic circuits

Q. The digital multiplexer is basically a combination logic circuit to perform the operation
A. AND-AND
B. OR-OR
C. AND-OR
D. OR-AND

AND-OR

Q. The output of NOR gate is
A. High if all of its inputs are high
B. Low if all of its inputs are low
C. High if all of its inputs are low
D. High if only of its inputs is low

High if all of its inputs are low

Q. How many lines the truth table for a four-input NOR gate would contain to cover all possible input combinations ?
A. 4
B. 8
C. 12
D. 16

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16

Q. A toggle operation cannot be performed using a single
A. NOR gate
B. AND gate
C. NAND gate
D. XOR gate

AND gate

Q. Which table shows the electrical state of a digital circuit’s output for every possible combination of electrical states in the inputs ?
A. Function table
B. Truth table
C. Routing table
D. ASCII table

Function table

Q. What is the minimum number of 2 input NAND gates required to implement the function F = (x’+y’) (z+w)
A. 6
B. 5
C. 4
D. 3

4

Q. How many truth tables can be made from one function table ?
A. One
B. Two
C. Three
D. Any numbers

Two

Q. A comparison between serial and parallel adder reveals that serial order
A. is slower
B. is faster
C. operates at the same speed as parallel adder
D. is more complicated

is slower

Q. What is the largest number of data inputs which a data selector with two control inputs can have ?
A. 2
B. 4
C. 8
D. 16

4

Q. If a logic gates has four inputs, then total number of possible input combinations is
A. 4
B. 8
C. 16
D. 32

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16

Digital electronics and logic design mcqs with answers pdf

Q. A combinational circuit is one in which the output depends on the
A. input combination at the time
B. input combination and the previous output
C. input combination at that time and the previous input combination
D. present output and the previous output

input combination at the time

Q. he function of a multiplexer is
A. to decode information
B. to select 1 out of N input data sources and to transmit it to single
channel
C. to transit data on N lines
D. to perform serial to parallel conversion

to select 1 out of N input data sources and to transmit it to single channel

Q. A combinational logic circuit which generates a particular binary word or number is
A. Decoder
B. Multiplexer
C. Encoder
D. Demultiplexer

Decoder

Q. Which of the following circuit can be used as parallel to serial converter ?
A. Multiplexer
B. Demultiplexer
C. Decoder
D. Digital counter

Multiplexer

Q. In which of the following adder circuits, the carry look ripple delay is eliminated ?
A. Half adder
B. Full adder
C. Parallel adder
D. Carry-look-ahead adder

Parallel adder

Q. Adders
A. adds 2 bits
B. is called so because a full adder involves two half-adders
C. needs two input and generates two output
D. All of these

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All of these

Q. The inverter OR-gate and AND gate are called deeision-making elements because they can recognize some input while disregarding others. A gate recognize a word when its output is
A. words,high
B. bytes,low
C. bytes,high
D. character,low

words,high

Q. Which one of the following set of gates are best suited for ‘parity’ checking and ‘parity’ generation.
A. AND, OR, NOT gates
B. EX-NOR or EX-OR gates
C. NAND gates
D. NOR gates

EX-NOR or EX-OR gates

Q. An AND circuit
A. is a memory circuit
B. gives an output when all input signals are present simultaneously
C. is a -ve OR gate
D. is a linear circuit

gives an output when all input signals are present simultaneously

Q. Which of the following adders can add three or more numbers at a time ?
A. Parallel adder
B. Carry-look-ahead adder
C. Carry-save-adder
D. Full adder

Carry-save-adder

Q. What is the difference between binary coding and binary-coded decimal?
A. BCD is pure binary.
B. Binary coding has a decimal format.
C. BCD has no decimal format.
D. Binary coding is pure binary.

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Binary coding is pure binary.

Q. Digital electronics is based on the __ numbering system.
A. decimal
B. octal
C. binary
D. hexadecimal

binary

Q. An informational signal that makes use of binary digits is considered to be:
A. solid state
B. digital
C. analog
D. non-oscillating

digital

Q. The 1’s complement of 10011101 is __.
A. 01100010
B. 10011110
C. 01100001
D. 01100011

01100010

Q. In the decimal numbering system, what is the MSD?
A. The middle digit of a stream of numbers
B. The digit to the right of the decimal point
C. The last digit on the right
D. The digit with the most weight

The digit with the most weight

Q. Which of the following statements does NOT describe an advantage of digital technology?
A. The values may vary over a continuous range.
B. The circuits are less affected by noise.
C. The operation can be programmed.
D. Information storage is easy.

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The values may vary over a continuous range.

Q. What are the symbols used to represent digits in the binary number system?
A. 0,1
B. 0,1,2
C. 0 through 8
D. 1,2

0,1

Digital electronics and logic design sppu mcq pdf

Q. NAND gate produces output HIGH, when
A. all the time
B. when any input is LOW
C. when any input is HIGH
D. when all inputs are HIGH

when any input is LOW

Q. Any number with an exponent of one is equal to:
A. zero.
B. one.
C. two.
D. that number.

that number.

Q. Determine the values of A, B, C, and D that make the sum term equal to zero.
A.A = 1, B = 0, C = 0, D = 0
B.A = 1, B = 0, C = 1, D = 0
C.A = 0, B = 1, C = 0, D = 0
D.A = 1, B = 0, C = 1, D = 1

A = 1, B = 0, C = 1, D = 0

Q. Which of the following expressions is in the sum-of-products (SOP) form?
A.(A + B)(C + D)
B.(A)B(CD)
C.AB(CD)
D.AB + CD

AB + CD

Q. One of De Morgan’s theorems states that . Simply stated, this means that logically there is no difference between:
A.a NOR and an AND gate with inverted inputs
B.a NAND and an OR gate with inverted inputs
C.an AND and a NOR gate with inverted inputs
D.a NOR and a NAND gate with inverted inputs

a NAND and an OR gate with inverted inputs

Q. The commutative law of Boolean addition states that A + B = A × B.
A.True
B.False

False

Q. The systematic reduction of logic circuits is accomplished by:
A.using Boolean algebra
B.symbolic reduction
C.TTL logic
D.using a truth table

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using Boolean algebra

Q. An AND gate with schematic “bubbles” on its inputs performs the same function as a(n)__ gate.
A.NOT
B.OR
C.NOR
D.NAND

NOR

Q. For the SOP expression , how many 1s are in the truth table’s output column?
A.1
B.2
C.3
D.5

3

Q. A truth table for the SOP expression has how many input combinations?
A.1
B.2
C.4
D.8

8v

Q. How many gates would be required to implement the following Boolean expression before simplification? XY + X(X + Z) + Y(X + Z)
A.1
B.2
C.4
D.5

5

Q. Determine the values of A, B, C, and D that make the product term equal to 1.
A. A = 0, B = 1, C= 0, D = 1
B. A = 0, B = 0, C = 0, D = 1
C. A = 1, B = 1, C = 1, D = 1
D. A = 0, B = 0, C = 1, D = 0

A = 0, B = 1, C= 0, D = 1

Q. Minterms are also called
A. standard sum
B. standard product
C. standard division
D. standard subtraction

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standard product

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Q. Maxterms are also called
A. standard sum
B. standard product
C. standard division
D. standard subtraction

standard sum

Q. What is the primary motivation for using Boolean algebra to simplify logic expressions?
A.It may make it easier to understand the overall function of the
circuit.
B.It may reduce the number of gates.
C.It may reduce the number of inputs required.
D.all of the above

It may reduce the number of gates.

Digital electronics and logic design sppu mcq pdf

Q. How many gates would be required to implement the following Boolean expression after simplification? XY + X(X + Z) + Y(X + Z)
A.1
B.2
C.4
D.5

4

Q. AC + ABC = AC
A.True
B.False

True

Q. Which Boolean algebra property allows us to group operands in an expression in any order without affecting the results of the operation [for example, A + B = B + A]?
A.associative
B.commutative
C.Boolean
D.distributive

commutative

Q. When grouping cells within a K-map, the cells must be combined in groups of __.
A.2s
B.1, 2, 4, 8, etc.
C.4s
D.3s

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1, 2, 4, 8, etc.

Q. Use Boolean algebra to find the most simplified SOP expression for F = ABD + CD + ACD + ABC + ABCD.
A.F = ABD + ABC + CD
B.F = CD + AD
C.F = BC + AB
D.F = AC + AD

F = ABD + ABC + CD

Q. Occasionally, a particular logic expression will be of no consequence in the operation of a circuit, such as a BCD-to-decimal converter. These result in __terms in the K-map and can be treated as either __ or , in order to the resulting term.
A. don’t care, 1s, 0s, simplify
B. spurious, ANDs, ORs, eliminate
C. duplicate, 1s, 0s, verify
D. spurious, 1s, 0s, simplify

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don’t care, 1s, 0s, simplify

Q. The NAND or NOR gates are referred to as “universal” gates because either:
A. can be found in almost all digital circuits
B. can be used to build all the other types of gates
C. are used in all countries of the world
D. were the first gates to be integrated

can be used to build all the other types of gates


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