30 most asked High performance computing mcq

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High performance computing mcq

high performance computing mcq questions and answers

1. Data hazards occur when

  1. Greater performance loss
  2. Pipeline changes the order of read/write access to operands
  3. Some functional unit is not fully pipelined
  4. Machine size is limited
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Pipeline changes the order of read/write access to operands

2. Systems that do not have parallel processing capabilities are 

  1. SISD
  2. SIMD
  3. MIMD
  4. All of the above
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SISD

3. How does the number of transistors per chip increase  according to Moore ´s law?  

  1. Quadratically     
  2. Linearly    
  3. Cubicly     
  4. Exponentially
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Exponentially

4. Parallel processing may occur 

  1. in the instruction stream   
  2. in the data stream   
  3. both[1] and [2]     
  4. none of the above

both[1] and [2]

5. Execution of several activities at the same time

  1. processing  
  2. parallel processing  
  3. serial processing   
  4. multitasking
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parallel processing

6. Cache memory works on the principle of        

  1. Locality of data    
  2. Locality of memory  
  3. Locality of reference    
  4. Locality of reference & memory
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Locality of reference

7. SIMD represents an organization that _________

  1. refers to a computer system capable of processing several programs at the same time.        
  2. represents organization of single computer containing a control unit, processor unit and a memory unit.        
  3. includes many processing units under the supervision of a common control unit          
  4. none of the above.

includes many processing units under the supervision of a common control unit

8. General MIMD configuration usually called 

  1. a multiprocessor   
  2. a vector processor   
  3. array processor    
  4. none of the above.
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a multiprocessor

9. MIMD stands for

  1. Multiple instruction multiple data   
  2. Multiple instruction memory data   
  3. Memory instruction multiple data   
  4. Multiple information memory data

Multiple instruction multiple data

10. M.J. Flynn’s parallel processing classification is based on:     

  1. Multiple Instructions  
  2. Multiple data   
  3. Both (a) and (b)    
  4. None of the above
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Both (a) and (b)

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11. The major disadvantage of pipeline is:   

  1. High cost individual dedicated  
  2. Initial setup time If branch instruction is encountered 
  3. the pipe has to be flushed     
  4. All of the above    
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the pipe has to be flushed

12. A topology that involves Tokens. 

  1. Star     
  2. Ring    
  3. Bus    
  4. Daisy Chaining

Ring

13. multipoint topology is       

  1. bus     
  2. star    
  3. mesh    
  4. ring    
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bus

14. In super-scalar mode, all the similar instructions are grouped and executed together.    

  1. TRUE    
  2. False

TRUE

15. Which mechanism performs an analysis on the code to determine which data items may become unsafe for caching, and they mark those items accordingly?     

  1. Directory protocol   
  2. Snoopy protocol    
  3. Server based cache coherence     
  4. Compiler based cache coherence
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Compiler based cache coherence

16. How many processors can be organized in 5-dimensional binary hypercube system?

  1. 25  
  2. 10  
  3. 32  
  4. 20  

32

17. Multiprocessors are classified as ________.  

  1. SIMD    
  2. MIMD    
  3. SISD   
  4. MISD

MIMD

18. Which of the following is not one of the interconnection structures? 

  1. Crossbar switch   
  2. Hypercube system     
  3. Single port memory  
  4. Time-shared common bus
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Single port memory

19. Which combinational device is used in crossbar switch for selecting proper memory from multiple addresses?

  1. Multiplexer    
  2. Decoder  
  3. Encoder     
  4. Demultiplexer  

Multiplexer

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20. How many switch points are there in crossbar switch network that connects 9 processors to 6 memory modules?  

  1. 50 
  2. 63  
  3. 60  
  4. 54
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54 (switch points = no. of processors * no. of memory modules)

21. In a three-cube structure, node 101 cannot communicate directly with node?   

  1. 1  
  2. 11  
  3. 100 
  4. 111

11

22. Which method is used as an alternative way of snooping-based coherence protocol?

  1. Directory protocol   
  2. Memory protocol    
  3. Compiler based protocol  
  4. None of above

Directory protocol

23. snoopy cache protocol are used in —————–based system  

  1. bus    
  2. mesh    
  3. star    
  4. hypercube   
bus mesh star hypercube

bus

24. superscalar architecture contains ————-execution units for instruction execution 

  1. multiple   
  2. single  
  3. none of the above   
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multiple

25. time taken by header of a message between two directly connected nodes is called as—————– 

  1. startup time   
  2. per hop time    
  3. per word transfer time  
  4. packaging time

per hop time

26. the number of switch requirement for a network with n input and n output is —– 

  1. n   
  2. n2  
  3. n3  
  4. n4  
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n2

27. which of the following is not static network

  1. bus    
  2. ring    
  3. mesh    
  4. crossbar switch 

crossbar switch

28. In super-scalar processors, ________ mode of execution is used.  

  1. In-order     
  2. Post order 
  3. Out of order    
  4. None of the mentioned   

Out of order

29. Which of the following is a combination of several processors on a single chip?      

  1. Multicore architecture  
  2. RISC architecture   
  3. CISC architecture   
  4. Subword parallelism

Multicore architecture

30. The important feature of the VLIW is …..       

  1. ILP 
  2. Cost effectiveness  
  3. performance 
  4. None of the mentioned   
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ILP

30. The important feature of the VLIW is …..       

  1. ILP 
  2. Cost effectiveness  
  3. performance 
  4. None of the mentioned   

ILP

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31. The parallel execution of operations in VLIW is done according to the schedule determined by …..   

  1. sk scheduler   
  2. Interpreter 
  3. Compiler    
  4. Encoder

Compiler

32. The VLIW processors are much simpler as they do not require of ….. 

  1. Computational register 
  2. Complex logic circuits  
  3. SSD slots   
  4. Scheduling hardware
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Scheduling hardware

33. The VLIW architecture follows ….. approach to achieve parallelism.

  1. MISD    
  2. SISD    
  3. SIMD    
  4. MIMD

MIMD

34. Which of the following is not a Pipeline Conflicts?       

  1. Timing Variations    
  2. Branching  
  3. Load Balancing  
  4. Data Dependency
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Load Balancing

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